The present invention relates to an electronic volume and more particularly, to an electronic volume which is improved to permit an easy change of rate of impedance variation in a variable impedance circuit.
Generally, an audio circuit incorporates various variable impedance circuits such as a bass control circuit, treble control circuit, balance control circuit and volume control circuit. Such a variable impedance circuits are usually composed of a variable resistor directly connected to the signal transmission path. In some cases, however, the variable impedance circuit is composed of a so-called electronic volume in which a variable resistor is connected out of the signal transmission path and an impedance circuit such as transistor connected to the signal transmission path is controlled by an electronic control signal.
FIG. 1 schematically shows the circuit arrangement of an example of known electronic volumes. In this figure, a reference numeral 1 denotes a variable impedance circuit for use in various controls of audio signals, e.g. a bass control, treble control, balance control and volume control. This variable impedance circuit is adapted to have its impedance varied by means of a control circuit 2 having two keys: namely, an up key 2u and a down key 2d. In the illustrated example, the control circuit 2 has a logical circuit 2b and an adder (adder/subtractor) 2a in addition to these keys 2u and 2d. A reference numeral 3 designates a hold/through gate the state of which is switchable by means of a change-over switch 3a between a hold state and a through state. In the through state, the hold/through gate 3 permits the signal from the adder 2a to pass therethrough in accordance with a clock signal, whereas, in the hold/through state, the hold gate 3 holds, as the control signal for the variable impedance circuit 1, the last input signal which has passed therethrough when the same is in the through state.
The signal which has passed the hold/through gate 3 is fed back to the adder 2a as an input to the A terminal of the latter. In the illustrated example, therefore, the adder 2a, i.e. the control circuit 2 adds or substracts 1 (one) in synchronization with the clock signal of the hold/through gate 3.
Assume here that the change-over switch 3a of the hold/through gate 3 has been switched to place the gate 3 into its through state and that a key, for example the up key 2u, is actuated. In consequence, the input to the B terminal of the adder 2a takes the logically "0" level while the input of the carry terminal of the adder 2a takes the logically "1" level, by the operation of the logic circuit 2b consisting of three elements. Consequently, 1 is added to the data (a) which has been stored in the adder 2a. Then, the new data (a)+1 obtained as a result of the addition is temporarily stored in the gate 3 and is then applied to a D-A converter 4 and the adder 2a.
The clock signal is delivered to the gate 3 at a predetermined period. If the up key 2u is pressed continuously, the data applied to the adder 2a and the D-A converter 4 are increased at each time a clock signal is received, and the impedance of the variable impedance circuit 1 is increased corresponding to the increase of the data. Thus, adjustment of the impedance is completed by stopping actuation of the up key 2u when the impedance of the variable impedance circuit 1 has reached the desired value while observing the display on the display device 6 which receives a signal from the logic circuit 2b through a pattern converter 5. To the contrary, the B terminal input and the carrier terminal input to the adder 2a take the "1" level and "0" level, respectively, as the down key 2d is actuated. The subtraction of the data is made in this case by the same principle as that for the addition. After the completion of the adjustment, of the impedance change-over switch 3 is closed to keep the gate 3 in the hold state, so that any undesirable change of impedance in the impedance circuit 1 attributable to an accidental actuation touch of the key 2u or 2d is avoided advantageously.
In the electronic volume 7 having the described construction, since the period of the clock signal applied to the gate 3 is fixed, an impractically long time may be required when the impedance has to be varied largely or, to the contrary, the aimed impedance variance is exceeded even by a short manipulation of the keys 2u or 2d when a delicate variation of the impedance is required.